FET memory technology has been devoted in the prior art to the storage of binary electric signals, as is disclosed, for example, in U.S. Pat. No. 3,728,696 to Polkinghorn. In the prior art binary FET read only memory, a plurality of address input lines and selection lines form a matrix with regions of a semiconductor substrate. Binary information is stored at locations between adjacent semiconductor regions by the presence or absence of field effect transistors at that location. Alternate semiconductor regions are selectively connected to a voltage reference and the remaining regions in between are selectively connected to a common output point by means of selection field effect transistors in series with each region. Selection signals applied to the selection transistors of an adjacent pair of regions connect one region to the voltage reference and the other region to output to provide a binary output signal which is a function of the data stored at a particular addressed storage location.
The direction of evolution for the semiconductor storage device technology has been to increase the number of storage devices per unit area on the semiconductor chip. This increases the storage capacity with respect to the cost of manufacture of the semiconductor memory.
In the course of the evolution of the semiconductor industry, the technique of ion-implantation into the channel region of an FET device has been developed to adjust the threshold voltage for the FET device so that the gate voltage at which the device will switch on can be customized in accordance with the application at hand. Techniques for accomplishing this have been disclosed in U.S. Pat. No. 3,873,372 to Johnson. In the case of an N-channel FET device, where the source and drain of N-type conductivity are formed in a substrate of P-type conductivity, the threshold voltage of the FET device may be increased by ion-implanting additional P-type conductivity dopants into the channel region. Alternately, the threshold voltage of the FET device may be reduced by ion-implanting N-type conductivity dopants into the channel region. The degree of change of the threshold voltage during ion-implantation is in approximate proportion to the dosage of the ion-implantation dopant in the channel region. This threshold voltage may be adjusted by controlling the ion-implantation beam current or the time of exposure to the ion beam, as well as by other processing factors.
In the prior art, support circuitry for a binary FET read only memory (ROM) has employed basic FET inverter circuits such as is described in U.S. Pat. No. 3,406,298 to Axelrod. Other types of prior art inverter circuits which can be employed in the support circuitry for the prior art binary read only memories is discussed in U.S. Pat. No. 4,072,868 by H. N. Kotecha, et al.